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Nano Scientific Research Centre Pvt Ltd
Nano Scientific Research Centre Pvt Ltd


VLSI DESIGN TRAINING

Nano Scientific Research Centre Pvt Ltd.,(AN ISO 9001 : 2008 CERTIFIED COMPANY)

Nano Scientific Research Center pvt ltd., is invloved in the design and development of electronic based systems and we do extensive research in dsp based embedded solutions for telecom,mobile applications & consumer electronics.we do offer

  • INDUSTRAIAL SERVICES
  • CORPORATE TRAINING
  • STUDENT TRAINING
  • ACADEMIC PROJECTS

Our trainers/developers have years of experience in teaching/training.Each of them have higher professional university degree and specializations.Students find that our instructors are well informed about the current technological developments,who don't restrict their knowledge imparting process with in the curriculum.


Advance Diploma Course In Asic Design & Verification

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Advance Diploma Course In Asic Design & Verification
Approx. Rs 30,000 / student
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ADVANCE DIPOLMA COURSE IN ASIC DESIGN & VERIFICATION
ADVANCE DIGITAL ELECTRONICS
Introduction to VLSI
ASIC Design Flow
Logic Gates
Number Systems and Code Conversions
K-maps
Combinational Logic Circuits
Sequential Logic Circuits
Flip-Flops
Counters
Registers
Finite State Machine
Memory Organizations
Programmable Logic Devices (FPGA’s)
LINUX
Introduction to Linux OS
Basics of Linux commands
Basics of Shell scripting
Basics of Perl scripting
VERILOG HDL
Introduction to Verilog HDL
Modeling Concepts
Gate Level Modeling
Data Flow Modeling
Behavioural Modeling
Structural Modeling
Switch Level Modeling
Data Types
Operators
Procedure and Flow Of Control Statement
Designing of Combinational Circuits
Designing of Sequential Circuits
FSM Design Modeling
Designing of Memories
Writing Testbench using Verilog
Task and Functions
System Tasks
Compiler Directives
Advance Nets in Verilog
Bus Functional Modeling
Verilog Based Assertions
Code Coverage.
SYSTEM VERILOG
Introduction to Verification Plan
Introduction to System Verilog
Data types
Procedural & Flow Control Statements
Semaphores
Events
Virtual Interfaces
Assertions
Arrays
Task And Functions
Interfaces and Clocking Block
Program Blocks
Fork – Join Statements
OOPS Concepts
Randomization and Constraints
Mailboxes
Functional Coverage
Packages
Writing Testbench in System Verilog
Project supported based on Methodology
Introduction to Methodology – UVM
EDA TOOLS
QuestaSim
Modelsim
Xilinx ISE
PHYSICAL DESIGN
Trends And Challenges In VLSI
ASIC Flow
Introduction of Transistors
Introduction of CMOS Technology
Stick Diagrams
Lambda – Rules
Layouts
STA (STATIC TIMING ANALYSIS)
Fundamentals of Delay calculations (wire modeling).
Setup/Hold Time definitions & Slack Calculations.
Different Timing Path Analysis.
Analysis & approach to minimize the timing violations.
STA Constraint development.
PLACE & ROUTE
Floor Planning
I/O Ring & Power Grid Planning
Placement Methodologies
CTS(Clock Tree Synthesis)
Routing & Timing Optimization
DFT (DESIGN FOR TESTABILITY)
Fault Models
ATPG Algorithms
At-Speed Testing
IDDQ Testing & Memory BIST
I/O Testing
Pattern Generation
ARCHITECTURE
SOC Bus Structure
SOC Processor Architecture
SOC peripherals
LOGIC DESIGN
FSM Design & FIFO Design
Handshaking Protocol’s
Math Function Implementation
Reset Design
Clock Management
EDA TOOLS
Micro Wind – Layout
DSCH – Schematics
H-Spice & Spice Language(optional)
  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Digital Electronics

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    Digital Electronics
    Approx. Rs 3,000 / Unit
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    Introduction to VLSI
    • Evolution of VLSI Systems

    • Applications of VLSI Systems

    • Processor Based Systems

    • Embedded Systems

    • FPGA Based Systems

    • Digital System Design Using FPGAs

    • Spartan-3 FPGAs

    • Introduction to VHDL language

     

    Digital Electronics

    • Introduction to Digital Electronics

    • Number systems

    • Code conversions

    • Arithmetic’s

    • Boolean algebra

    • Logic gates

     

    Combinational logic design

    • Standard representation of logical functions

    • Karnaugh map method

    • MSI circuits

    • Multiplexers/demultiplexers

    • Adders / subtractors

    • Arithmetic Logic Unit (ALU)

    • Encoders/ Decoders

     

     

     

    Flip Flops

    • Flip-flops

    • Type of Flip flops

    • Conversion of flip flops

    • Application of flip flops

     

    Sequentional circuit design

    • Registers

    • Types of shift registers

    • Application of registers

    • Counters

    • Ripple or Asynchronous counters

    • Synchronous counters

    • Clocked sequential circuits

     

    Designing of Memories

     

    • Introduction

    • Memory Organization and operation

    • Expanding memory size

    • Expanding memory capacity

    • Different types of memories

     

    Programmable Logic devices

     

    • Introduction

    • Programmable logic array (PLAs)

    • Programmable array logic (PALs)

    • Complex programmable logic devices (CPLDs)

    • Field programmable gate array (FPGA)

    • Computer-Aided Design Tools (CAD)

  • Minimum Order Quantity: 1 Unit
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    VHDL Training

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    VHDL Training
    Approx. Rs 6,500 / student
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    Circuit Design with VHDL

     

    • Introduction to VHDL

    • Code structure

    • Library Functions

    • Entity

    • Architecture

    • Configuration Declaration

    • Package Declaration

     

     

    Elements of VHDL LANGUAGES

     

    • Different Data types

    • Operators

    • Attributes

    • Generic

    • Identifiers

    • Variables & Signals

     

    Different types of VHDL Modeling

     

    • Behavioral modeling

    • Modeling techniques

    • If statement

    • Case statement

    • Wait statement

    • Loop statement

    • Process statement

     

     

     

    Dataflow modeling

     

    • When statements.

    • Block statement

    • Generate statement

     

    Structural Modeling

     

    • Component declaration

    • Component instantiation

    Test Bench

    • Modeling a Test Bench

    • Test Bench for Combinational Circuits

    • Test Bench for Sequential Circuits

     

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Verilog Training

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    Verilog Training
    Approx. Rs 6,500 / student
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    Design and synthesis by using Verilog HDL

     

    Introduction to Verilog HDL

     

    • Evolution of CAD

     

    • Typical Design flow

     

    • Importance of HDL's

     

    • Popularity of Verilog HDL

     

    Modeling Concepts

     

    • Design methodologies

     

    • Module concept

     

    • types of modeling

    Basic Concepts

     

    • Lexical Conventions

     

    • Number Specifications

     

    • Strings

     

    • Data Types

     

    • System Task

     

    • Compiler Directives

     

    Modules

     

    • List of Ports

     

    • Port Declaration

     

    • Port Connection Pins

     

     

    Gate Level Modeling

     

    • Different Types of Gates

     

    • Gate Delays

     

     

    Data Flow modeling

     

    • Continous Assignments

     

    • Delays

     

    • Epression Operators

     

    • Operators Types

     

     

    Behavioural Modeling

     

    Structured Procedures

     

    Intial Statement

     

    Always Statement

     

    Event- Base Timing Control

     

    Conditional Statements

     

    If Statements

     

    Case Statements

     

    Loop Statements

     

    Task and Functions

     

    • Different between Task and Function

     

    • Function

     

    • Task

     

    Switch Level Modeling(optional)

     

    Labs

     

    • Introduction to XILINX tools

    • Entering HDL code

    • Synthesis and implementation

    • Creating Test Bench

    • Simulation

    • Physical Realization

     

     

    ABOUT PROJECT:

     

    • Project Basics, Module Explanation

    • Presentation basics

    • Report preparation guide lines

     

     

    PRESENTATION:

     

    • Introduction to Project

    • Block Diagram

    • Scope of work

    • Schematic Diagram and Explanation

    • Software Flow chart

    • Tools used

    • Applications

    • Advantages and Limitations

    • Simulation results

    • Conclusion

     

     

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    System Verilog Design

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    System Verilog Design
    Approx. Rs 12,000 / student
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    SYSTEM VERILOG:

    ??? Introduction to Verification Plan
    ??? Introduction to System Verilog
    ??? Data types
    ??? Procedural & Flow Control Statements
    ??? Semaphores
    ??? Events
    ??? Virtual Interfaces
    ??? Arrays
    ??? Task And Functions
    ??? Interfaces and Clocking Block
    ??? Program Blocks
    ??? Fork – Join Statements
    ??? OOPS Concepts
    ??? Randomization and Constraints
    ??? Mailboxes
    ??? Functional Coverage
    ??? Packages
    ??? Writing Testbench in System Verilog
    ??? Project supported based on Methodology
    Introduction to Methodology – UVM
    EDA TOOLS
    ??? QuestaSim
    ??? Modelsim
    ??? Xilinx ISE
  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Physical Design Training

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    Physical Design Training
    Approx. Rs 10,000 / student
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    PHYSICAL DESIGN

    Trends And Challenges In VLSI
    ASIC Flow
    Introduction of Transistors
    Introduction of CMOS Technology
    Stick Diagrams
    Lambda – Rules
    Layouts
    STA (STATIC TIMING ANALYSIS)
    Fundamentals of Delay calculations (wire modeling).
    Setup/Hold Time definitions & Slack Calculations.
    Different Timing Path Analysis.
    Analysis & approach to minimize the timing violations.
    STA Constraint development.
    PLACE & ROUTE
    Floor Planning
    I/O Ring & Power Grid Planning
    Placement Methodologies
    CTS(Clock Tree Synthesis)
    Routing & Timing Optimization
    DFT (DESIGN FOR TESTABILITY)
    Fault Models
    ATPG Algorithms
    At-Speed Testing
    IDDQ Testing & Memory BIST
    I/O Testing
    Pattern Generation
    ARCHITECTURE
    SOC bus Structure
    SOC Processor Architecture
    SOC peripheralsLOGIC DESIGN
    FSM Design & FIFO Design
    Handshaking Protocol’s
    Math Function Implementation
    Reset Design
    Clock Management
    EDA TOOLS
    Micro Wind – Layout
    DSCH – Schematics
    H-Spice & Spice Language(optional
  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    VLSI IEEE Projects Mtech & B.tech 2017

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    VLSI IEEE Projects  Mtech & B.tech 2017
    Approx. Rs 8,000 / Person
    Get Best Quote

    VLSI IEEE Projects Mtech & Btech 2017 For more Projects Papers contact us Mallikarjun - 8297578555

    NV1601

    Floating-Point Butter???y Architecture Based on Binary Signed-Digit Representation (2016)

     

    NV1602

    FlexibleDSP Accelerator Architecture Exploiting Carry-Save Arithmetic(2016)

     

    NV1603

    Utilizing Shared Memory Multi-cores to Speed-up the ATPG process(2016)

     

    NV1604

    Fault Tolerant Parallel Filters Based on Error Correction Codes(2016)

     

    NV1605

    Error Correction Technique Based on Modular Correcting Codes(2016)

     

    NV1606

    FPGA Based Rate Compatible LDPC Codes for The Next Generation of Optical Transmission Systems(2016)

     

    NV1607

    A Modified Partial Product Generator for Redundant Binary Multipliers(2016)

     

    NV1608

    A High-Throughput Energy-Ef???cient Implementation of Successive Cancellation Decoder for Polar(2016)

     

    NV1609

    On Optimization-based ATPG and its Application for Highly Compacted Test Sets(2016)

     

    NV1610

    High-Performance Pipelined Architecture of Elliptic Curve Scalar Multiplication Over GF(2m) (2016)

     

    NV1611

    Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks(2016)

     

    NV1612

    A High-Throughput Energy-Ef???cient Implementation of Successive Cancellation Decoder for Polar(2016)

     

    NV1613

    Low-Power Parallel Chien Search Architecture Using a Two-Step Approach(2016)

     

    NV1614

    Memory-Reduced Turbo Decoding Architecture Using NII Metric Compression Logic(2016)

     

    NV1615

    A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO(2016)

     




     

  • Minimum Order Quantity: 1 Person
  • Yes! I am interested

     
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