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Nano Scientific Research Centre Pvt Ltd
Nano Scientific Research Centre Pvt Ltd


LOW POWER VLSI IEEE PROJECTS

2015 M.Tech LIVE Projects (Embedded Linux, VLSI,DIP/DSP/SIMULINK)

Nano Scientific Research Centre Pvt Ltd.,(AN ISO 9001 : 2008 CERTIFIED COMPANY)

Nano scientific research center pvt ltd -
is one of the leading top training and consulting services provider in hyderabad with a good placement track record. We will provide "regular training, fast track training, online training with job assurance. We are providing exclusive training on projects. Faculty from top mnc’s with highly skilled domain expertise will train & guide you with real time examples, project explanation. We also help you in resume preparation and provide job assistance until you get job
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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled

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40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled
Approx. Rs 10,000 / student
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  • Aim: The main aim of this project is to design “40-Gb/s 0.7-V 2:1 MUX and 1:2 DEMUX with Transformer-Coupled Technique for SerDes Interface”

    Abstract:

    This paper explores the use of transformer-coupled (TC) technique for the 2:1 MUX and the 1:2 DEMUX to serialize-and-deserialize (SerDes) high-speed data sequence. The widely used current-mode logic (CML) designs of latch and multiplexer/demultiplexer (MUX/DEMUX) are replaced by the proposed TC approach to allow the more headroom and to lower the power consumption. Through the stacked transformer, the input clock pulls down the differential source voltage of the TC latch and the TC multiplexer core while alternating between the two-phase operations. With the enhanced drain-source voltage, the TC design attracts more drain current with less width-to-length ratio of NMOS than that of the CML counterpart. The source-offset voltage is decreased so that the supply voltage can be reduced. The lower supply voltage improves the power consumption and facilitates the integration with low voltage supply SerDes interface. The MUX and the DEMUX chips are fabricated in 65-nm standard CMOS process and operate at 0.7-V supply voltage. The chips are measured up to 40-Gb/s with sub-hundred mill watts power consumption.

    Existing system:

     

    Proposed System:

     

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

    References:

    [1] Home page of the IEEE 802.3b a 40 Gb/s and 100 Gb/s Ethernet Task Force, , Apr. 2010 [Online]. Available: http://grouper.IEEE.org/ groups/ 802/3/ba/public/index.html Std

    [2] G. Ono, K. Watanabe, T . Muto, H. Yamashita, K. Fukuda, N. Masuda, R. Nemoto, E. Suzuki, T. Takemoto, F. Yuki, M. Yagyu, H. Toyoda, M. Kono, A. Kambe, S. Umai, T. Saito, and S. Nishimura, “A 10:4 MUX and 4:10DEMUXGea rbox LSI for 100-gigabit ethernet link,” IEEE J. Solid-State Circuits, vol. 46, no. 12, pp. 3101–3112, Dec. 2011.

  • Minimum Order Quantity: 1 student
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    A 90nm Low Power OTA Using Adaptive Bias

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    A 90nm Low Power OTA Using Adaptive Bias
    Approx. Rs 10,000 / student
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    Aim: The main aim of this project is to design “A 90nm Low Power OTA Using Adaptive Bias”.

    Abstract:

    Low power class AB operational transconductance amplifier (OTA)which is fully differential operating at low voltage 0.4 V supply designed in low cost 90nm technology is proposed in this paper. Differential pairs such as P channel and N channel with complementary input configuration are used in input stage to achieve input common mode range (ICMR) which is full rail to rail. For increasing slew rate without sacrificing power consumption adaptive bias circuits are used hence amplifier works in class AB. The common mode feed forward circuit (CMFF) is employed for maximizing common mode rejection ratio (CMRR). To make system power efficient whole amplifier operates in weak inversion region. After designing layout of an op amp, Simulation with parasitic is carried out and shows that DC gain of 51.15 dB, 876.5 kHz unity gain bandwidth (UGB)with 77.7º phase margin for 10 pF capacitive load and slew rate of 0.1 V/µs; CMRR and PSRR are 116.9 and 97.30 dB respectively. The proposed OTA dissipates very less power of 4.78 µW and shows ability to use in applications where less energy is mandatory.

    Existing system:

     

     

     

    Disadvantages:

    · Slew rate is low

    · Power consumption is high

    · Performance speed is low

    Proposed System:

     

    Slew rate is 4 or 5 times larger than existing circuit
    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

     

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    A Fully Integrated Low Dropout Regulator

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    A Fully Integrated Low Dropout Regulator
    Approx. Rs 10,000 / student
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    Aim: the main aim of this project is to design “a low- voltage low-dropout regulator ”
    Abstract:
    A low-voltage low-dropout (ldo) regulator that converts an input of 1 v to an output of 0.85–0.5 v, with 90-nmcmos technology is proposed. A simple symmetric operational transconductance amplifier is used as the error amplifier (ea), with a current splitting technique adopted to boost the gain. This also enhances the closed-loop bandwidth of the ldo regulator. In the rail-to-rail output stage of the ea, a power noise cancellation mechanism is formed, minimizing the size of the power mos transistor. Furthermore, a fast responding transient accelerator is designed through the reuse of parts of the ea. These advantages allow the proposed ldo regulator to operate over a wide range of operating conditions while achieving 99.94% current efficiency, a 28-mv output variation for a 0–100 ma load transient, and a power supply rejection of roughly 50 db over0–100 khz. The area of the proposed ldo regulator is only0.0041 mm2, because of the compact architecture.
    Existing system:
    Fig:the single-transistor-control ldo based on the fvf topology. Fig: the fvf based ldo with inserted buffer.
    Proposed system:
    Fig: proposed ldo circuit
    Tools: h – spice tool, micro wind, digital schematic.
    References:
    [1] m. Jeong et al., “a 65 nm cmos low-power small-size multistandard, multiband mobile broadcasting receiver soc, ” in ieee int. Solid-state circuits conf. Dig. Tech. Papers (isscc), feb. 2010, pp. 460–461.
  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    A VLIW Architecture for Executing Multi-Scalar

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    A VLIW Architecture for Executing Multi-Scalar
    Approx. Rs 10,000 / student
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    /Vector Instrument

    AIM:

    The main aim of the project is to design “A VLIW Architecture for Executing

    Multi-Scalar/Vector Instructions on Unified Datapath”.

    (ABSTRACT)

    This paper proposes new processor architecture for accelerating data-parallel applications based on the combination of VLIW and vector processing paradigms. It uses VLIW architecture for processing multiple independent scalar instructions concurrently on parallel execution units. Data parallelism is expressed by vector ISA and processed on the same parallel execution units of the VLIW architecture. The proposed processor, which is called VecLIW, has unified register file of

    64x32-bit registers in the decode stage for storing scalar/vector data. VecLIW can issue up to four scalar/vector operations in each cycle for parallel processing a set of operands and producing up to four results. However, it cannot issue more than

    one memory operation at a time, which loads/stores 128-bit scalar/vector data from/to data cache. Four 32-bit results can be written back into VecLIW register file. The complete design of our proposed VecLIW processor is implemented using Verilog targeting the Xilinx FPGA Virtex-5, XC5VLX110T-3FF1136 device.

    Proposed Architecture:

    Advantage:

    VecLIW executes multi-scalar and vector instructions on the same parallel execution datapath. VecLIW has a modified five-stage pipeline for (1) fetching 128-bit VLIW instruction (four individual instructions), (2) decoding/reading operands of the four instructions packed in VLIW, (3) executing four operations on parallel execution units, (4) loading/storing 128-bit (4×32-bit scalar/vector) data from/to data memory, and (5)writing back 4×32-bit scalar/vector results.

    BLOCK DIAGRAM: 

     

    VecLIW datapath for executing multi-scalar/vector instructions

     

    TOOLS: Xilinx ISE 12.2

    REFERENCE:

    [1] J. Hennessay and D. Patterson, Computer Architecture A Quantitative

    Approach, 5th ed, Morgan-Kaufmann, September 2011.

    [2] J. Mike, Superscalar Microprocessor Design, Prentice Hall (Prentice

     

    Hall Series in Innovative Technology), 1991.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    An 8 GHz First-Order Frequency Synthesizer for Low-Power

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    An 8 GHz First-Order Frequency Synthesizer for Low-Power
    Approx. Rs 10,000 / student
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    Aim: The main aim of this project is to design “An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation”

    Abstract:

    This paper presents a low-power ???rst-order frequency synthesizer architecture suitable for high-speed onchip clock generation. The proposed design features an architecture combining an LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, a phase interpolator, digital coarse-tuning and rotational frequency detection for ???ne-tuning. Similar to multiplying delay-locked loops (MDLLs), this architecture limits jitter accumulation to one reference cycle, as jitter during one reference cycle does not contribute to the next reference cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, the reference clock edge is injected by phase inter polation to support higher frequencies and lower jitter. Functionality of the frequency synthesizer is validated between 8–9.5 GHz, LC VCO's range of operation. First-order dynamic of the acquisition has been analyzed and demonstrated through measurement. The output clock at 8 GHz has an integrated rms jitter of 490 fs, peak-to-peak periodic jitter of 2.06 ps and total rms jitter of 680 fs. Different components of jitter have been analyzed and separate measurements have been done to support the analysis. The reference spurs are measured to be 64.3 dB below the carrier frequency. At 8GHz the system consumes 2.49mW from a 1V supply.

    Existing System:

     

    Figure 1 Conventional multiplying PLL (MPLL).

    Proposed System:

     

    Figure 3 Proposed first – order frequency synthesizer

    Tool: H – SPICE Tool, Micro Wind, Digital Schematic.

    Reference:

    [1] P. Hanumolu, B. Casper, and R. Mooney, “Analysis of PLL clock jitter in high-speed serial links,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 50, no. 11, pp. 879–886, Nov. 2003.

    [2] J. Crossley, E. Naviasky, and E. Alon, “An energy-ef???cient ring-oscillator digital PLL,” in Proc. IEEE Custom Int. Circuits Conf., 2010, pp. 1–4.

    [3] M. Hossain et al., “A 6.4/3.2/1.6 Gb/s low power interface with all digital clock multiplier for on-the-???y rate switching,” in Proc. IEEE Custom Int. Circuits Conf. (CICC), 2012, pp. 1–4.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    An Efficient Design Technique for Low Power Dynamic Feedthro

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    An Efficient Design Technique for Low Power Dynamic Feedthro
    Approx. Rs 10,000 / student
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    Aim: The main aim of this project is to design “An Efficient Design Technique for Low Power Dynamic Feed through Logic with Enhanced Performance for wide fan-in gates”

    Abstract:

    This paper presents a new approach to high performance and low power circuit for wide fan-in gates using a new CMOS logic known as feedthrough logic (FTL). Feedthrough logic can improve the performance by partial valuation in its computational block before getting a valid input. The FTL is more suited for those circuits which consists of a critical path of large cascaded inverting gates. FTL based circuits can perform better in both high fan-out and high frequency operations due to both dynamic power consumption and lower delay at the cost of area. The proposed circuit achieves a reduction in the average power. The comparison analysis has been carried out by simulating the logic circuit by 180 nm technology. The proposed modified FTL reduces total power consumption up to 13.25% in wide fan-in NAND gates and 99.9% in wide fan-in NOR gates. This model works more effectively in the case of NOR gates but creates more delay as compared to other proposed FTL models.

    Existing System:

     

    Proposed System:

     

    Tools: H – SPICE Tools, Micro Wind, Digital Schematic.

    References:

    [1] J.M. Rabaey, A. Chandrakasan, B. Nikolic, ‘Digital Integrated Circuits: A Design perspective’ 2e Prentice-Hall, Upper saddle River, NJ, 2002.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Comparative Performance Analysis of XOR XNOR Function Based

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    Comparative Performance Analysis of XOR XNOR Function Based
    Approx. Rs 10,000
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    AIM:

    The main aim of the project is to design “Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Full Adder Circuits”.

    (ABSTRACT)

    CMOS Design, Complimentary Pass Transistor Logic Design and papers presents the realization of full adder designs using Complimentary XOR-XNOR Design in a single unit. The main motive of this paper is to determine the comparative study of power, delay, power delay product(PDP) of different Full adder designs using CMOS Logic Styles. Simulations results clearly determine that XOR-XNOR type Full adder Design is better compared to Complimentary CMOS style and Pass Transistor Design with respect to power, delay. Power Delay Product Comparison. The power delay product is also important parameter to determine the performance of the design. The XORXNOR implementation provides better performance and requires less number of transistors compared to other full adder design.

    Proposed Architecture:

    In this paper we can implement 8 Bit RCA by using the full adder in exciting paper These RAC are for fast addition

     

     

    Advantage:

    Ø Implementation of different adder logic styles includes Complimentary CMOS, EXOR- EXNOR, Complementary Pass Transistor Logic

    Ø New adder design of EXOR-EXNOR based adder cell with less power, delay, and power delay product (PDP).

    BLOCK DIAGRAM: 

     

     

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:

    [I] J. M. Rabaey, A. Chandrakasan, B. Nikolic, "Digital Integrated Circuits, A design Perspective," 2nd Prentice Hall, Englewood CI iffs, NJ, 2002.

     

    [2] J. Uyemura, "CMOS LogicCircuitDesign,"Kluwer, 1999.

     

    [3] Sung-Mo Kang, Y. Leblebici, "CMOS Digital Integrated Circuits: Analysis and Design," Tata McGraw Hill, 2003.

     

    [4] N. Weste, D. Harris, " CMOS VLSI Design," Pearson Wesley, 2005.

     

    [5] R . P e d r a m , M . P e d r a m , L o w P o w e r D e s i g n

    Methodologies, KI uwer, Norwell, MA, 1996

     

    Yes! I am interested

    Design Low Power Conditional Pulse Control with Transmission

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    Design Low Power Conditional Pulse Control with Transmission
    Approx. Rs 10,000 / student
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    • Aim: The main aim of this project is to design “Low Power Conditional Pulse Control with Transmission Gate Flip-Flop”

       

      Abstract:

      In this paper, a low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using TSMC CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO) by 8.2% in data-to-Q delay. In the mean time, the performance edges on power and power- delay-product metrics are 22.7% and 29.7%, respectively.

      Existing System:

       

      (b) (c)

      Fig. 1. (a) Conditional pulse enhancement scheme FF (b) Signal feed through scheme FF (c) MHLFF

      Proposed System:

       

      Fig. 2. Proposed CPCTG-FF

       

      Tool: H – SPICE tool, Micro Wind, Digital Schematic.

       

       

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Design Methodology of Sub threshold Three-Stage CMOS OTA

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    Design Methodology of Sub threshold Three-Stage CMOS OTA
    Approx. Rs 10,000 / student
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      • Aim: The main aim of this project is to design “Design Methodology of Sub threshold Three-Stage CMOS OTAs Suitable for Ultra-Low-Power Low-Area and High Driving Capability”

        Abstract:

        A design methodology for three-stage CMOS OTAs operating in the sub threshold region is presented. The procedure is focused on the development of ultra-low-power ampli???ers requiring low silicon area but being able to drive high capacitive loads. Indeed, by following the presented methodology we designed aCMOSOTAina0.35µm technology that occupies only 4.4*10-3, is powered with a 1-V supply, exhibits 120-dB DC gain and is able to drive a capacitive load up to 200 pF. Thanks to proposed methodology, the OTA is able to provide a 20-kHz unity gain bandwidth while consuming 195 W, even under the high load considered. Moreover, the slew rate enhancer circuit in addition to the class AB output stage allows an average slew rate higher than with the 200 pF load. Comparison with prior art shows an improvement factor in the ???gures of merit higher than 5.

        Existing system:

         

        Dis-advantage :

        1) High power consumption

        2) slew-rate is low

         

        Proposed System:

         

        Fig: proposed diagram

        Advantages:

        1. less power consumption

        2. High speed of operation

        3. High slew-rate

         

        Extension:

        · Adoptive with common gate technique by this speed increases.

        Tool: H – SPICE Tool, Micro Wind, Digital Schematic.

        References:

        [1] J. Guo and K. N. Leung, “A CMOS voltage regulator for passive RFID tag ICs,” Int. J. Circuit Theor. Appl, vol. 40, no. 4, pp. 329–340, Apr. 2012.

        [2] B.H.Calhoun,D.C.Daly,N.Verma,D.F.Finchelstein,D.D.Wentzloff, A. Wang, S. Cho, and A. P. Chandrakasan, “Design considerations for ultra-low energy wireless microsensor nodes ,” IEEE Trans. Comput., vol. 54, no. 6, pp. 727–740, Jun. 2005.

        [3] A. Tabesh and L. G. Fréchette, “A low-power stand-alone adaptive circuit for harvesting energy from a piezoelectr ic micropower generator,” IEEE Trans. Ind. Electron., vol. 27, no. 3, pp. 740–749, Mar. 2010.Practicing.
    Yes! I am interested

    Design Of Logic Circuits With Adaptive Feedback Equalization

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    Design Of Logic Circuits With Adaptive Feedback Equalization
    Approx. Rs 10,000 / Piece
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    Aim: The main aim of this project is ” design of logic circuits with adaptive feedback equalization to get tunable sub threshold voltage”.

    Abstract:

    Low energy has become one of the primary constraint in the design of digital VLSI circuits in recent years. Minimum-energy consumption can be achieved in digital circuits by operating in the sub-threshold regime. However, in this regime process variation can result in up to an order of magnitude variations in Ion/Ioff ratios leading to timing errors, which can have a detrimental impact on the functionality of the sub-threshold circuits. These timing errors become more frequent in scaled technology nodes where process variations are highly prevalent. Therefore, mechanisms to mitigate these timing errors while minimizing the energy consumption in sub-threshold circuits are required. In this paper, we propose the use of a variable threshold feedback equalizer circuit with sequntial logic blocks to mitigate the timing errors, which can then be leveraged to reduce the dominant leakage energy by scaling supply voltage or decreasing the propagation delay. At the fixed supply voltage, we can decrease the propagation delay of the critical path using equalizer circuits and, correspondingly decrease the leakage energy consumption. We also present detailed energy-performance models of the adaptive feedback equalizer circuit. As part of the modeling approach, we also develop an analytical methodology to estimate the equivalent resistance of MOSFET devices in sub threshold regime. For a 64-bit adder designed in 130 nm, our proposed approach can reduce the normalized variation of the critical path delay from 16.1% to 11.4% while reducing the energy-delay product by 25.83% at minimum energy supply voltage.

    Existing system:

     

     

     

    (b)buffer-inserted nonequalized design.

    Dis advantages:

    Ø The circuit cannot be operate at sub threshold region when the leakage is occurred in the circuit

    Ø Performance is low

    Ø Power consumption is high

    Proposed system:

     

    Advantages:

    Ø Here the circuit can be operated in sub threshold region also

    Ø Performance increases

    Ø Power consumption is low

    Tools: H – SPICE Tool, Micro Wind, Digital Schematic.

     

  • Minimum Order Quantity: 1 Piece
  • Yes! I am interested

    Free Class Ab Ab Miller Opamp With High Current Enhancement

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    Free Class Ab Ab Miller Opamp With High Current Enhancement
    Approx. Rs 10,000 / student
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    • IEEE Embedded Projects on ARM9/11/CORTEX-A8/ZYNQ ZYBO
    • Real Time Ieee 2015 Projects On Embedded Systems (B.Tech/M.Tech,B.E/M.E)

      Micro controllers / Processors:

      • Arm7, Arm9, Arm11, Arm Cortex-a8,ZYNQ ZYBO7000
      • Avr, Pic, Psoc, Arduino, Freescale

      Languages:

      • C/c
      • Embedded C
      • Assembly Language
      • Perl
      • Python

      Softwares :
      • Linux - Ubuntu
      • Linux - Android
      • Linux - Fedora
      • Linux - Wince
      • Qt - Creator
      • vivado
      • Rtos
      • Rt Linux
      • Keil
      • Proteus
      • Flashmagic
      • Orcad
      • Express Pcb
      • Eagle
      Hardware :
      • Beagle Bone Series
      • Raspberry Pi Series
      • Friendlyarm Samsung
      • Atmel, Atmega Series
      • Arduino Series
      • 3g Module, Wifi, Zigbee, Gprs
      • Ecg, Eeg, Spo2, Fprs, Usb Camera
      • Gsm, Rfid, Rf, Rf Pro
      Domains :
      • Wireless Sensor Networks
      • Dip Embedded Applications
      • Dsp Embedded Applications
      • Wireless Communications
      • Tele Communications
      • Touch Screen
      • Robotics
      • Biomedical
      • Security
      • Aerospace
      • Control Panel
      • Industrial Automation
      • Control Systems, Etc.
      Our Training Features :
      • 100% Outputs With Extension
      • Paper Publishing In International Level
      • Project Training Session Are Conducted By Real-time Instructor With Real-time Examples.
      • Best Project Training Material .
      • State-of-the-art Lab With Required Software For Practicing.
  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Implementing Low-Power Dynamic Adders in MTCMOS Technology

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    Implementing Low-Power Dynamic Adders in MTCMOS Technology
    Approx. Rs 10,000
    Get Best Quote

    Aim: The main aim of this project is to design “Implementing Low-Power Dynamic Adders in MTCMOS Technology”

     

    Abstract:

    New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized by 94% to 96%. Simulation results verify that the circuits operate with high speed due to the low-VT transistors used in the evaluation block and also achieve a significant reduction in leakage power. The ground bouncing noise of the eight bit MTCMOS TSPC adder is also evaluated. It is shown that the ground bouncing noise of the circuit reduces with increase in sleep signal rise delay.

     

    Existing System:

     

    Figure 1. A cascaded dynamic logic block

     

    Proposed System:

     

    Figure 2. Proposed MTCMOS TSPC Adder Cell

     

    Figure 3. Proposed MTCMOS Domino Adder Cell

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

    Reference:

    [1] Gielen, G. ; Dehaene, W. "Analog and digital circuit design in 65 nm CMOS: end of the road?” IEEE Proceedings on Design, Automation and Test in Europe, 2005, Page(s): 37 - 42

    [2] V. Kursun and E. G. Friedman, “Node Voltage Dependent Subthreshold Leakage Current Characteristics of Dynamic Circuits,” Proceedings of the IEEE/ACM International Symposium of Quality Electronic Design, pp. 104-109,March 2004.

    [

    Yes! I am interested

    Low- Power Dual Dynamic Node Pulsed Hybrid Flip-flop

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    Low- Power Dual Dynamic Node Pulsed Hybrid Flip-flop
    Approx. Rs 10,000
    Get Best Quote

    AIM:

    The main aim of the project is to design “Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic”.

     

    (ABSTRACT)

    A new dual dynamic node hybrid flip-flop (DDFF) and a novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs eliminate the large capacitance present in the precharge node of several state-of-the-art designs by following a split dynamic node structure to separately drive the output pull-up and pull down transistors. The aim of the DDFF-ELM is to reduce pipeline overhead. It presents an area, power, and speed efficient method to incorporate complex logic functions into the flip-flop. The leakage power and process-voltage-temperature variations of various designs are studied in detail and are compared with the proposed designs. Also, DDFF and DDFF-ELM are compared with other state-of-the-art designs by implementing a 4-b synchronous counter and a 4-b Johnson up-down counter. The performance improvements indicate that the proposed designs are well suited for modern high-performance designs where power dissipation and latching overhead are of major concern

    Proposed Architecture:

    We can Implement the low power techniques like sleepy stack, sleepy keeper which will reduce dynamic power . To all the circuits in the paper.

    Advantage:

    Ø An analysis of the overlap period required to select proper pulse width was provided in order to make the design process simpler. The proposed DDFF eliminates the redundant power dissipation present in the XCFF.

    Ø By eliminating the charge sharing, the revised structure of the proposed flip-flop, DDFF-ELM, is capable of efficiently incorporating complex logic in to the flip-flop. The presented ELM outperforms the SDFF in the CLK driving power and in internal power dissipation.

    BLOCK DIAGRAM: 

     

     

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:

    [1] H. Patrovi, R. Burd, U. Salim, F. Weber, L. Di Gregorio, and D. Draper, “Flow-through latch and edge-triggered flip-flop hybrid elements,” in Proc. IEEE ISSCC Dig. Tech. Papers, Feb. 1996, pp. 138–139.

    [2] F. Klass, “Semi-dynamic and dynamic flip-flops with embedded logic,” in Proc. Symp. VLSI Circuits Dig. Tech. Papers, Honolulu, HI, Jun. 1998, pp. 108–109.

    Yes! I am interested

    Low-Power Clock Distribution Using a Current-Pulsed Clocked

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    Low-Power Clock Distribution Using a Current-Pulsed Clocked
    Approx. Rs 10,000
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    The Fastest Fourier Transform in the South

    Aim: The main aim of this project is to design “Low-Power Clock Distribution Using a Current-Pulsed Clocked Flip-Flop”

    Abstract:

    We propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signaling has been used in one-to-one signals, this is the ???rst usage in a one-to-many clock distribution network. To accomplish this, we create a new high performance current-mode pulsed ???ip-???op with enable (CMPFFE) using 45 nm CMOS technology. When the CMPFFE is combined with a CM transmitter, the ???rst CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks.

     

    Existing system:

     

     

    Fig.1. Previous CM schemes used an expensive trans- impedance amp Rx which could result in signi???cant skew due to VCM shift if applied to CDNs

     

    Disadvantage:

    · More delay

    · More Average Power Consumption

    Proposed system:

     

     

    Fig(a) proposed system with current mode flip-flop

    Advantages:

    · Less Average Power Consumption

    · Less Delay

    Extension:

    · Hybrid technique By this speed increases.

     

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

     

     

     

     

    References:

    [1] H.Zhang, G.Varghese, and J.M.Rabaey, “Lowswingon-chipsig- naling techniques: Effectiveness and robustness,” IEEE Trans. VeryLarge Scale Integr. (VLSI) Syst., vol. 8, no. 3, pp. 264–272, Jun. 2000.

    [2] C. Anderson, J. Petrovick, J. Keaty, J. Warnock, G. Nussbaum, J. Tendier, C.Carter, S.Chu, J.Clabes, J.DiLullo, P.Dudley, P.Harvey, B. Krauter, J. LeBlanc, P.-F. Lu, B. McCredie, G. Plum, P. Restle, S. Runyon, M. Scheuermann, S. Schmidt, J. Wagoner, R. Weiss, S.Weitzel, and B. Zoric, “Physical design of a fourth-generation power ghz microprocessor,” in Proc. ISSCC, Feb. 2001, pp. 232–233.

    [3] D. Sylvester and C. Hu, “Analytical modeling and characterization of deep-sub micrometer interconnect,” Proc. IEEE, vol. 89, no. 5, pp. 634–664, May 2001.

    [4] A. Katoch, H. Veendrick, and E. Seevinck, “High speed current-mode signaling circuits for on-chip interconnects,” in Proc. ISCAS, May 2005, pp. 4138–4141.

    Yes! I am interested

    Low-Voltage, Full-Swing Voltage-Controlled Oscillator With S

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    Low-Voltage, Full-Swing Voltage-Controlled Oscillator With S
    Approx. Rs 10,000 / student
    Get Best Quote

    Aim: The main aim of this project is to design “Low-Voltage, Full-Swing Voltage-Controlled Oscillator With Symmetrical Even-Phase Outputs Based on Single-Ended Delay Cells”.

    Abstract:Implementing a symmetrical even-phase ring-type voltage-controlled oscillator (VCO) is dif???cult when using a full-swing single-ended delay cell; however, the full-swing characteristic of this architecture improves the signal-to-noise ratio. Conventional symmetrical even-phase output VCOs require tail current circuits to implement differential delay stages. Therefore,full-swing requirements make conventional symmetrical even-phase output VCOs impractical. This paper proposes a new CMOS VCO. In addition, it can achieve wide tuning range, full-swing, even-phase outputs, and less supply voltage using the proposed single-ended delay stage. Moreover, its simple topology features multiple output phases and linear frequency voltage characteristics. The proposed topology was validated in a four-stage VCO operated at at 1.8 V of the supply voltage in a Taiwan Semiconductor Manufacturing Company 0.18-µm RF CMOS process.

    Existing system:

     

     

    Fig.1:.Single-ended delay cell circuit.

    Disadvantage:

    · More delay

    · More Average Power Consumption

    Proposed system:

     

     

    Fig.2: Proposed single-ended delay cell circuit

    .

    Fig.3. Proposed four-stage ring VCO based on single-ended delay cells.

    Advantages:

    · Less Average Power Consumption

    · Less Delay
    EXTENSION:Technology reduction
    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

    References:[1] C.-L. Yang, C.-L. Tsai, K.-T. Cheng, and S.-H. Chen, “Low-invasive implantable devices of low-power consumption using high-ef???ciency antennas for cloud health care,” IEEE Trans. Emerg. Sel. TopicsCircuitsSyst., vol. 2, no. 1, pp. 14–23, Mar. 2012.

     

     

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Power Efficient Class AB Op Amps With High and Symmetrical S

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    Power Efficient Class AB Op Amps With High and Symmetrical S
    Approx. Rs 10,000 / student
    Get Best Quote

    AIM:The main aim of the project is to design “Power Efficient Class AB Op-AmpsWith High and Symmetrical Slew Rate”.

    ABSTRACT:

    In this paper ,various class AB two-stage op-amps with high and approximately symmetrical slew rate and very simple architecture is proposed A current replicating branch with scaled-down transistors in combination with adaptive loads is used to implement a push–pull output stage with maximum output current several times higher than the bias current. Postlayout simulation and measurement results are presented and verify a 400%–500% slew rate and 80%–100% GB enhancement with only 5% additional quiescent power dissipation and 20% silicon area increase.

    Proposed Architecture:

    Advantage:

    Inclusion of adaptive loads in the current replicating branch instead of the input stage is advantageous in terms of offset.the proposed architecture achieve approximately symmetrical and high slew rate with very small additional static

    power dissipation and small additional circuitry.

    BLOCK DIAGRAM: 

     

    Class AB two-stage op-amp

    with current replicating branch using an adaptive load.

     

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:

    [1] J. Ramirez-Angulo and M. Holmes, “Simple technique using local

    CMFB to enhance slew rate and bandwidth of one-stage CMOS

    op-amps,” Electron. Lett., vol. 38, no. 23, pp. 1409–1411, Nov. 2002.

    [2] A. J. López-Martín, S. Baswa, J. Ramirez-Angulo, and R. G. Carvajal,

    “Low-voltage super class AB CMOS OTA cells with very high slew

    rate and power efficiency,” IEEE J. Solid-State Circuits, vol. 40, no. 5,

    pp. 1068–1077, May 2005.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Recursive Approach To The Design Of A Parallel Self-timed Ad

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    Recursive Approach To The Design Of A Parallel Self-timed Ad
    Approx. Rs 10,000
    Get Best Quote

    Aim: The main aim of this project is to design “Recursive Approach to the Design of a Parallel Self-Timed Adder”

    Abstract:

    This brief presents a parallel single-rail self-timed adder.It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using an industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders.

    Existing system:

     

    Fig.1. Ripple carry adder

    Disadvantage:

    · More delay

    · More Average Power Consumption

    Proposed system:

     

    Advantages:

    · Less Average Power Consumption

    · Less Delay

    Extension:

    · Technology reduction

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

     

    References:

    [1] D. Geer, “Is it time for clockless chips? [Asynchronous processor chips],” IEEE Comput., vol. 38, no. 3, pp. 18–19, Mar. 2005.

    Yes! I am interested

    A High Speed Binary Floating Point Multiplier

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    A High Speed Binary Floating Point Multiplier
    Approx. Rs 10,000 / student
    Get Best Quote

    Mtech Vlsi Ieee 2014 Projects

    Specialized On M.tech Vlsi Designing(frontend & Backend)

    Domains:

    • Processor Architecture
    • Bist Algorithms
    • Signal Processing
    • Image & Video Processing
    • Communication & Bus Protocols
    • Low Power Vlsi
    • Physical Design (250nm-180nm-90nm-45nm-32nm)
    • Fpga Prototyping, Etc...,

    Languages:

    • Vhdl
    • Verilog Hdl
    • System Verilog
    • H-spice

    Softwares :

    • Xilinx Ise
    • Xilinx Platform Studio
    • Tanner Eda
    • Dsch
    • Modelsim Ise
    • Microwind
    • Questasim
    • Pspice

    Hardwares :

    Spartan Series
    Vertex Series
    Altera Cyclone Series

    Our Training Features :
    100% Outputs With Extension
    Paper Publishing In International Level
    Project Training Session Are Conducted By Real-time Instructor With Real-time Examples.
    Best Project Training Material .
    State-of-the-art Lab With Required Software For Practicing.
    Yes! I am interested

    An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout

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    An Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout
    Approx. Rs 10,000 / student
    Get Best Quote

    Aim: The main aim of this project is to “Design of an Ultralow-Power Fast-Transient Capacitor-Free Low-Dropout Regulator With Assistant Push–Pull Output Stage.”

    Abstract: An output capacitor-free low-dropout regulator (LDO) using a class-AB operational amplifier and an assistant push–pull output stage (APPOS) circuit to enable fast-transient response with ultralow-power dissipation is presented in this brief. The APPOS circuit is proposed to deliver an extra current that is directly proportional to the output current of the class-AB operational amplifier during transient state with an automatic on/off feature. Moreover, the small-signal and large-signal responses of LDO can be separately optimized. As a result, transient performances of LDO are improved significantly without requiring an area-consuming on-chip capacitor anymore. The proposed LDO has been implemented in a standard 0.35-μm CMOS process. Experimental results show that the LDO can regulate the output voltage at 1.0 V from a 1.2-V supply voltage for the maximum load current of 100 mA. The output voltage fully recovers within 2.7 μs with the load current switching from 100 μA to 100 mA at a 1.2-μA quiescent current.

    Existing System:

     

    Fig: LDO with capacitor 

    Disadvantage:

    1)High droping nature

    2) High power consumption

    3) performance decreases.

    Proposed System:

     

    Fig: proposed LDO without Capacitor

    ADVANTAGES:

    1)Low droping nature

    2) Low power consumption

    3) performance increases

    Tools: H – SPICE Tool, Micro Wind, Digital Schematic.

    References:

    [1] M. Jeong et al., “A 65 nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC,” in IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers (ISSCC), Feb. 2010, pp. 460–461.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Analysis and Design of a Low-Voltage Low-Power Double-Tail C

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    Analysis and Design of a Low-Voltage Low-Power Double-Tail C
    Approx. Rs 10,000 / student
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    AIM:

    The main aim of the project is to design “ Low-Voltage Low-Power Double-Tail Comparator”.

    (ABSTRACT)

    The need for ultra low-power, area efficient, and high speed analog-to-digital converters is pushing toward the use of dynamic regenerative comparators to maximize speed and power efficiency. An analysis on the delay of the dynamic comparators is presented in this paper and analytical expressions are derived. From the analytical expressions, designers can obtain an intuition about the main contributors to the comparator delay and fully explore the trade offs in dynamic comparator design. Based on the presented analysis, a new dynamic comparator is proposed, where the circuit of a conventional double-tail comparator is modified for low-power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors, the positive feedback during the regeneration is strengthened, which results in remarkably reduced delay time. the proposed dynamic comparator can significantly reduce both the power consumption and delay time. The maximum clock frequency of the proposed comparator can be increased .

    Proposed Architecture:

    In this paper we can implement low power techniques to reduce the power consumption form the exciting by applying techniques like Dual stack, Dual sleep .

     

    Advantage:

     

    COMPARATOR is one of the fundamental building blocks in most analog-to-digital converters (ADCs). Many high speed ADCs, such as flash ADCs, require high-speed, low power comparators with small chip area. High-speed comparators in ultra deep sub micrometer (UDSM) CMOS technologies

    BLOCK DIAGRAM:

    Schematic diagram of the proposed dynamic comparator

    (a) Main idea.

     

    (b) Final structure.

     

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:

    [1] B. Goll and H. Zimmermann, “A comparator with reduced delay time in

    65-nm CMOS for supply voltages down to 0.65,” IEEE Trans. Circuits

    Syst. II, Exp. Briefs, vol. 56, no. 11, pp. 810–814, Nov. 2009.

    [2] S. U. Ay, “A sub-1 volt 10-bit supply boosted SAR ADC design in

    standard CMOS,” Int. J. Analog Integr. Circuits Signal Process., vol. 66,

     

    no. 2, pp. 213–221, Feb. 2011.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Carbon Nanotubes Blowing New Life into NP Dynamic CMOS

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    Carbon Nanotubes Blowing New Life into NP Dynamic CMOS
    Approx. Rs 10,000
    Get Best Quote

    Aim:
    The main aim of the project is to design “carbon nano tubes blowing new life into np dynamic cmos circuits”
    .
    (abstract)
    Low-power, compact, and high-performance np dynamic cmos circuits are presented in this paper assuming a 16 nm carbon nano tube transistor technology. The performances of two-stage pipeline 32-bit carry look ahead adders are evaluated based on hspice simulation with the following four different implementations: silicon mosfet (si-mosfet) domino logic, si-mosfet np dynamic cmos, carbon nano tube mosfet (cn-mosfet) domino logic, and cn-mosfet np dynamic cmos. While providing similar propagation delay, the total area of cn-mosfet np dynamic cmos adder is reduced
    Proposed architecture:
    .
    Advantage:
    Ø the well-known area and power consumption disadvantages of the np dynamic cmos circuits are eliminated by employing a carbon nanotube transistor technology.
    Ø the cn-mosfet np dynamic cmos circuit effectively suppresses both dynamic switching and leakage power consumption while providing similar propagation delay and miniaturizing the area as compared to both silicon and carbon nanotube domino logic circuits.
    .
    Block diagram:
    Top-view of a cn-mosfet. Static cmos inverter with cn-mosfets
    A multi-stage np dynamic cmos pipeline with carbon nanotube transistors
    Tools: hspice_va-2008.03, t-spice
    Reference:
    [1] v. Kursun and e. G. Friedman, multi-voltagecmos circuit design. New york, ny, usa: wiley, 2006.
    [2] s. B.Wijeratne, n. Siddaiah, s. K.Mathew, m. A. Anders, r. K. Krishnamurthy,
    J. Anderson, m. Ernest, and m. Nadine, “a 9-ghz 65-nm intel pentium processor integer execution unit, ” ieee j. Solid-state circuits, vol. 42, no. 1, pp. 26–37, jan. 2007.
    Yes! I am interested

    Design Of High Speed Ternary Full Adder And Three Input Xor

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    Design Of High Speed Ternary Full Adder And Three Input Xor
    Approx. Rs 10,000
    Get Best Quote

    Aim: The main aim of this project is to design “Design of high speed ternary full adder and three input XOR circuits using CNTFETs”

    Abstract:

    This paper proposes a new high speed ternary full adder (TFA) cell for carbon nano tube field effect transistor (CNTFET) technology. The proposed design has a symmetric pull-up and pull- down networks along with a resistive voltage divider as its integral part, which is configured using transistors. The design takes inputs through a decoding unit and uses ternary nature of A & B but inherent binary nature of Cin leading to simplicity in design. The design demonstrates high driving power and robustness in terms of insusceptibility to voltage and temperature variations. The sum generation unit of proposed design is further modified for achieving an energy efficient three-input ternary XOR circuit which can be used as a basic cell in modern circuit design. Hspice simulation results with 32nm Stanford CNTFET model show 49% reduction in delay with 19% progress in power delay product (PDP) for the proposed TFA and 43% reduction in delay with 48% improvement in PDP for the proposed three input ternary XOR circuit in comparison with the CNTFET-based designs, recently published in the literature.

    Existing System:

     

    Figure1 Conventional Full Adder

    Proposed System:

     

    Figure2 Schematic diagram of Proposed CNTFET-based TFA cell

    Tool: H – SPICE Tool, Micro Wind, Digital Schematic.

    References:

    [1] K.Roy, S.Mukhopadhyay, H. Meimand-Mehmoodi, “Leakage current mechanisms and leakage reduction techniques in deep-submicron CMOS circuits,” in Proc. IEEE, Feb.2003,vol.91,no. 2, pp. 305–327.

    [2] S. A. Tawfik, Z. Liu, and V. Kursun, “Independent-gate and tied-gate FinFET SRAM circuits: Design guidelines for reduced area and enhanced stability,” in Proc. Int. Conf. Microelectron. (ICM), Dec. 2007, pp. 171–174.

    [3] I. O’Connor, J. Liu, F. Gaffiot, F. Pregaldiny, C. Lallement, C. Maneux, J. Goguet, S. Fregonese, T. Zimmer, L. Anghel, “CNTFET Modeling and Reconfigurable Logic-Circuit Design,” IEEE Trans. Circuits Syst I Regul. vol. 54, no.11,pp. 2365–2379, Nov. 2007.

    band,” IEEE Des. Test. Comput., vol. 25, no. 2, pp. 178–186, Mar./Apr. 2008.

     

    Yes! I am interested

    Design Of Long Carry Chain Adders Using Cmos Technology To G

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    Design Of Long Carry Chain Adders Using Cmos Technology To G
    Approx. Rs 10,000 / No
    Get Best Quote

    Aim: The main of this project is to “Design of long carry chain adders using CMOS technology to get ultra-low power consumption.”

     

    Abstract:Power consumption of digital systems is an important issue in Nano scale technologies and growth of process variation makes the problem more challenging. In this brief we analyzed the throughput and sensitivity parameters by using different adder structures. In this we propose different adders with high throughput and with reduced sensitivity and also with low power consumption. The proposed adder structures are designed with CMOS technology. Therefore, our proposed solution to improve the throughput loss while reducing sensitivity to process variations is using simpler elements in deep pipelined designs or massively parallel structures.

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

    Advantages of tool:

    · More flexible

    · More reliable

    · We see both AC and DC Analysis

    · We can see fabrication steps of MOSFETs

  • Minimum Order Quantity: 1 No
  • Yes! I am interested

    Design Of Low Power Shift Register Using Pulsed Latches

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    Design Of Low Power Shift Register Using Pulsed Latches
    Approx. Rs 10,000 / student
    Get Best Quote

    Aim: The main aim of this project is to design “Design of low power shift register using pulsed latches” by using CMOS technology.

    Abstract:

    The timing elements and clock interconnection Networks such as flip-flops and latches, is One of the most power consuming components in modern very large Scale integration (VLSI) system. The area, power and transistor count will compared and designed using several latches and flip flop stages. Flip Flop is a circuit which is used to store state information. Power consumption is one of the main objectives in designing a flip flop. The flip flops used in designing are Hybrid Latch Flip Flop (HLFF), explicit- pulsed data-close-to-output flip-flop (ep-DCO) and Adaptive-Coupling Redundant Flip-Flop (ACFF). Compare pulse triggered latches based on transistor count, power and layout area. Constructing shift registers by using conditional capture pulsed latches instead of normal flipflops, because a pulsed latch is much smaller than a flip-flop. All the latches and flip flop designs are made by using 90nm technology. A 256-bit shift register using pulsed latches wasfabricatedusinga0.18µm CMOS process with VDD = 1.8 V. The core area is 6600µm2. The power consumption is 1.2 mW at a 100 MHz clock frequency. The proposed shift register saves 37% area and 44% power compared to the conventional shift register with ???ip-???ops.

    Proposed System:

     

    Fig: proposed diagram with delay clock

     

    Advantages:

    1)average power decreases

    2)speed increases

    Extension:

    · This is done in 90nm technology

    · By this speed increases

    · Performance increases.

    Tool: H – SPICE Tool, Micro Wind, Digital Schematic.

    References:

    [1] P.Reyes, P.Reviriego, J.A.Maestro, and O.Ruano, “Newprotection techniques against SEUs for moving average ???lters in a radiation environment,” IEEE Trans. Nucl. Sci., vol. 54, no. 4, pp. 957–964, Aug. 2007.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Design Of Quadded Logic And Quadded Transistor Using Low Pow

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    Design Of Quadded Logic And Quadded Transistor Using Low Pow
    Approx. Rs 10,000 / student
    Get Best Quote

    AIM:

    The main aim of the project is to design “Design of Quadded logic and quadded transistor using low power consumption”.

    ABSTRACT:

     

    Advances in CMOS technology have made digital circuits and systems very sensitive to manufacturing variations, aging and/or soft errors. Fault-tolerant techniques using hardware redundancy have been extensively investigated for improving reliability. Quadded Logic (QL) is an interwoven redundant logic technique that corrects errors by switching them from critical to subcritical status; however, QL cannot correct errors in the last one or two layers of a circuit. In contrast to QL, quadded transistor (QT) corrects errors while performing the function of a circuit. In this paper, a technique that combines QL with QT is proposed to take advantage of both techniques. The proposed QLQT technique is evaluated and compared with other fault-tolerant techniques such as triple modular redundancy (TMR) and triple interwoven redundancy (TIR), using stochastic computational models (SCMs). Simulation results show that QLQT has a better reliability than the other fault-tolerant techniques (except in the very restrictive case of small circuits with low gate error rates and very short paths from primary inputs to primary outputs). These results provide a new insight for implementing efficient fault-tolerant techniques in the design of reliable circuits and systems

    Existing method:

     

     

    Triple model redundancy circuit diagram

    Disadvantages:

    Ø When leakage is occur errors cannot detected

    Proposed method:

     

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

    REFERENCES :

    [1] International Technology Roadmap for Semiconductors, 2012.

     

    [2] W. Rao, C. Yang, R. Karri, and A. Orailoglu, "Toward future systems with nanoscale devices: Overcoming the reliability challenge," Computer 44, no. 2 (2011): 46-53.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Design of a Low Power 4x4 Multiplier Based on Five Transisto

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    Design of a Low Power 4x4 Multiplier Based on Five Transisto
    Approx. Rs 10,000
    Get Best Quote

    Aim: The main aim of this is to “Design of a Low Power 4x4 Multiplier Based on Five Transistor(5-T) Half Adder, Eight Transistor (8-T) Full Adder & Two Transistor (2-T) AND Gate”.

    Abstract:

    In this paper we propose a new technique for implementing a low power high speed multiplier using full adder consisting of minimum no. of transistors (8-T). Multiplier circuits are used comprehensively in Application Specific Integrated Circuits (ASICs). Thus it is desirable to have high speed operation for the sub components. The explored method of implementation achieves a high speed low power design for the multiplier. Simulated results indicate the superior performance of the proposed technique over conventional CMOS multiplier. Detailed comparison of simulated results for the conventional and present method of implementation is presented.

    Existing System:

     

    Figure: Conventional Full Adder

    Disadvantes:

    · Area increases

    · Performance speed is slow

    · High power consumption

     

    Proposed System:

    Figure: 8-T FA based on MUX&XOR gates

    Advantages:

    · Area decreases

    · High speed performance

    · Low power consumption

    Tool: H – SPICE tool, Micro Wind, Digital Schematic.

    References:

    [1] Y.Berg, M. Azadmehr,"Novel ultra low-voltage and high-speed CMOS pass transistor logic", Proceedings of the IEEE, Faible Tension FaibleConsommation (FTFC),Paris, 2012

    [2] Hung Tien Bui, Yuke Wang and Ying Tao Jiang, “Design and Analysis of low Power 10 Transistor Full adders Using Novel XOR/XNOR gates”, IEEETransactions on Circuits And Systems- II, : Analog and Digital SignalProcessing, Vol.49,No.1 January 2002

    Yes! I am interested

    Dynamic Threshold Source Coupled Logic with Pushpull topolog

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    Dynamic Threshold Source Coupled Logic with Pushpull topolog
    Approx. Rs 10,000 / student
    Get Best Quote

    AIM:

    The main aim of the project is to design “Dynamic Threshold Source Coupled Logicwith Pushpull topology for Ultra Low Power Applications”.

     

    (ABSTRACT)

    Subthreshold source coupled logic circuits (STSCL) are normally used for designing ultra-low power components and systems operating in the weak inversion (subthreshold) regime. This paper presents an implementation of a robust source coupled technique i.e. Dynamic threshold source coupled logic (DTSCL) with push pull amplifier at the output stage. The proposed circuit was analyzed to obtain minimum delay and power dissipation by varying the tail bias current. This circuit offered a very low power delay product (PDP) and was less sensitive to temperature and power supply variations. A tail bias current of the order of Pico amperes was capable of driving the circuit when implemented on 180nm CMOS technology. Measured results indicate that the simulated circuit offers a better performance for ultra-low power SCL circuits. Cadence

    virtuoso and Spectre simulation tools were used for simulating the circuit.

    Existing Architecture:

     

    praposed Architecture:

     

    Advantages:

    Power consumption is low

    TOOLS: hspice,microwind,digital schematic

    REFERENCE:

    [1] Tajalli and Y. Leblebici, “Leakage Current Reduction Using Sub-Threshold Source-Coupled Logic,” IEEE Trans- actions on Circuits and SystemsII: Express Briefs, Vol. 56, No. 5, 2009, 374-378.

    [2] Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz, “Sub-Threshold Source-Coupled Logic Circuits for Ultra- Low Power Applications,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 7,2008, 1699-1710.

    >[2] Tajalli, E. J. Brauer, Y. Leblebici and E. Vittoz, “Sub-Threshold Source-Coupled Logic Circuits for Ultra- Low Power Applications,” IEEE Journal of Solid-State Circuits, Vol. 43, No. 7,2008, 1699-1710.

     

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Enhanced Area Efficient Architecture for 128 bit Modified C

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    Enhanced Area Efficient Architecture for 128 bit  Modified C
    Approx. Rs 10,000 / student
    Get Best Quote

    AIM:

    The main aim of the project is to design “Enhanced Area Effi cient Architecture for 128 bit Modified CSLA”.

    (ABSTRACT)

    In the design of Integrated circuits, area occupancy plays a vital role because of increasing necessity of portable systems. Carry Select Adder (CSLA) is a fast adder used in dataprocessing processors for performing fast arithmetic functions.

    From the structure of the CSLA, the scope is to reduce the area of CSLA based on the efficient gate-level modification. In this paper 128 bit Regular Linear CSLA, Modified Linear CSLA, Regular Square-root CSLA (SQRT CSLA) and Modified SQRT CSLA architectures have been developed and compared. However, the

    Regular CSLA is still area-consuming due to the dual RippleCarry Adder (RCA) structure. For reducing area, the CSLA can be implemented by using a single RCA and an add-one circuit instead of using dual RCA. Comparing the Regular Linear CSLA with Regular SQRT CSLA, the Regular SQRT CSLA has reduced area as well as comparing the Modified Linear CSLA with Modified SQRT CSLA; the Modified SQRT CSLA has reduced area. The results and analysis show that the Modified Linear CSLA and Modified SQRT CSLA provide better outcomes than

    the Regular Linear CSLA and Regular SQRT CSLA respectively.This project was aimed for implementing high performance optimized FPGA architecture. Xilinx ISE 12.2 Simulator is used for simulating the CSLA and synthesized using Xilinx PlanAhead13.4.Then the implementation is done in Virtex5 FPGA Kit.

    Proposed Architecture:

    Advantage:

    The reduced number of gates of this work offers the great advantage in the reduction of area. The area of the proposed design shows a decrease for 16-bit, 32-bit, 64-bit and 128-bit sizes which indicate the success of the method and not a

    mere tradeoff of delay for area. The Modified CSLA architecture is therefore, low area, simple and efficient for VLSI hardware implementation.

    BLOCK DIAGRAM: 

     

    Modified 16-bit SQRT CSLA

     

    Modified 16-bit Linear CSLA

     

    TOOLS: Xillinx ISE 12.2

    REFERENCE:

    [1] 0.1. Bedrij, "Carry-select adder, " IRE Trans. Electron.Computer., pp. 340-344, 1962.

    [2] B. Ramkumar, H.M. Kittur, and P. M. Karman, "ASIC implementation of modified faster carry save adder, "Eur. J. Sci. Res., vol. 42, no. 1, pp.53-58, 2010.

    [3] T. Y. Ceiang and M. 1. Hsiao, "Carry-select adder using single ripple Carry adder, " Electron. Lett, vol. 34, no.22, pp. 2101-2103, Oct. 1998.

     

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal

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    Low-Power Pulse-Triggered Flip-Flop Design Based on a Signal
    Approx. Rs 10,000 / student
    Get Best Quote

    AIM:

    The main aim of the project is to design “Low-Power Pulse-Triggered Flip-Flop Based on a Signal Feed-Through Scheme”.

    (ABSTRACT)

    A low-power flip-flop (FF) design featuring an explicit type pulse-triggered structure and a modified true single phase clock latch based on a signal feed-through scheme is presented. The proposed design successfully solves the long discharging path problem in conventional explicit type pulse-triggered FF (P-FF) designs and achieves better speed and power performance. Based on post-layout simulation results using BISM4 Model CMOS 90-nm technology, the proposed design outperforms the conventional P-FF design data-close-to-output (ep-DCO).

    In the mean time, the performance edges on power and power- delay-product metrics are improved.

    Proposed Architecture:

    .We can Implement the low power techniques like sleepy stack, sleepy keeper which will reduce dynamic power . And further we can implement shift registers by using these flip flops

    Advantage:

    As we provide a signal feed through from input source to the internal node of the latch,it would facilitate extra driving to shorten the transition time and enhance both power and speed performance.The design was intelligently achieved by employing a simple pass transistor.

    BLOCK DIAGRAM: 

    Schematic of the proposed P-FF design

     

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:

    [1] H. Kawaguchi and T. Sakurai, “A reduced clock-swing flip-flop (RCSFF)

    for 63% power reduction,” IEEE J. Solid-State Circuits, vol. 33, no. 5,

     

    pp. 807–811, May 1998.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Novel Class of Energy-Efficient Very High-Speed Conditional

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    Novel Class of Energy-Efficient Very High-Speed Conditional
    Approx. Rs 10,000 / student
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    AIM:

    The main aim of the project is to design “Novel Class of Energy-Efficient Very High-Speed Conditional Push–Pull Pulsed Latches”.

    (ABSTRACT)

    In this paper, a new class of pulsed latches is presented and experimentally assessed in 65-nm CMOS. Its conditional push–pull pulsed latch topology is based on a push–pull final stage driven by two split paths with a conditional pulse generator. Two circuit implementations of the concept are discussed, with their main difference being in the pulse generator, which can be either shared (CSP3L) or not (CP3L).Measurements show that the proposed topology is very fast,as it outperforms the well-known transmission gate pulsed latch (TGPL) by 1.5×–2×; hence the proposed pulsed latch has the highest performance ever reported. The proposed pulsed latch is also shown to significantly improve the energy efficiency compared to the state of the art. Indeed, improvement in ED3 product (energy × delay3) over TGPL was found for designs targeting minimum ED3. For designs targeting minimum ED,improvement was found in ED product. This comes at the cost of a 1.15×−1.35× cell area penalty, which translates into an overall area increase well below 1% in typical systems.Measurements on 256 replicas confirm that the above benefits are kept in the presence of variations. Accordingly, the proposed class of pulsed latches goes beyond the current state of the art and is well suited for VLSI systems that require both high performance and energy efficiency.

    Proposed Architecture:

    Advantage:

     

    Push–pull final stage and split paths in the first stage enable a significant reduction in path and parasitic effort. proposed topologies are fastest ever reported. More importantly, the energy efficiency of the proposed pulsed latches enables a significant improvement beyond the state of the artFinally, the CP3L and CSP3L were shown to be equivalent in terms of energy and performance, hence both topologies are equally worth considering when designing highly energyefficient

    systems..

    BLOCK DIAGRAM: 

     

    General scheme of the proposed class of pulsed latches

     

    TOOLS: hspice_vA-2008.03, t-spice

    REFERENCE:

    [1] S. Naffziger and G. Hammond, “The implementation of the nextgeneration

    64b itanium microprocessor,” in Proc. IEEE ISSCC,

     

    Feb. 2002, pp. 276–504.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Period Extension and Randomness Enhancement Using High-Throu

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    Period Extension and Randomness Enhancement Using High-Throu
    Approx. Rs 10,000 / student
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    AIM:

    The main aim of the project is to achieve“Period Extension and Randomness Enhancement Using High-Throughput Reseeding-Mixing PRNG”.

    (ABSTRACT)

    In this paper ,we present a new reseeding-mixing method to extend the system period length and to enhance the statistical properties of a chaos-based logistic map pseudo random number generator (PRNG). The reseeding method removes the short periods of the digitized logistic map and the mixing method extends the system period length by ???XOring??? with a DX generator. When implemented in the TSMC 0.18-μm 1P6M CMOS process, the new reseeding-mixing PRNG (RM-PRNG) attains the best throughput rate of 6.4 Gb/s compared with other nonlinear PRNGs. In addition, the generated random sequences pass the NIST SP 800-22 statistical tests including ratio test and U-value test

    Proposed Architecture:

    Advantage:

    The proposed hardware implementation of RM-PRNG offer long periods and high throughput rate while adhering to established statistical standards for PRNGs. the hardware cost is reduced and the hardware efficiency increases. In addition, the high throughput rate (>6.4 Gb/s) is attained because RM-PRNG can generate multiple random bits in an iteration. With all these advantages, the proposed nonlinear RM-PRNG can a good candidate for potential applications in test pattern generation, telecommunication system and even cryptography if the security issue can be addressed properly.

    BLOCK DIAGRAM: 

     

    Structure of the proposed RM-PRNG.

     

    TOOLS: Xilinx ISE 12.2

    REFERENCE:

    1. J. E. Gentle, Random Number Generation and Monte CarloMethods,2nded.NewYork:Springer-Verlag, 2003.

     

    2. M. P. Kennedy, R. Rovatti, and G. Setti, Chaotic Electronics in Telecommunications. Boca Raton, FL: CRC, 2000.

     

    3. D. Knuth, The Art of Computer Programming, 2nd ed. Reading, MA: Addison-Wesley, 1981.

     

    4. A). Klapper and M. Goresky, ???Feedback shift registers, 2-adic span, and combiners with memory,??? J. Cryptology, vol. 10, pp. 111–147, 1997.

     

    5. D. H. Lehmer, ???Mathematical methods in large-scale computing units,??? in Proc. 2nd Symp. Large Scale Digital Comput. Machinery, Cambridge, MA, 1951, pp. 141–146, Harvard Univ. Press.

  • Minimum Order Quantity: 1 student
  • Yes! I am interested

    Design and Implementation of Multi-Mode QCLDPC Decoder

    Design and Implementation of Multi-Mode QCLDPC Decoder
    Approx. Rs 10,000 / student
    Yes! I am interested



     
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